@X @~
~V7 56 2 -5
~D10
~H                    MUSS
~
~
~D10
~H             AP7211
~D10
~MMANCHESTER UNIVERSITY  -  CONFIDENTIAL
@X @~
~V7 56 2 -5
~D10
~H                    MUSS
~
~
~D10
~H             AP7211
~D10
~MMANCHESTER UNIVERSITY  -  CONFIDENTIAL
~
~
~V2 -16
                                                                     ISSUE 9~
~V2 0
~V9 -1
~P
~V9 1
~YAP7211
~S1~M~LAP7 IMPLEMENTATION DESCRIPTION~
~S1~M~LSection 21 Version 1~
~S1~LSection 21.1 Bootstrap~
~S1~L1. General Description~
~BThis module provides the bootstrap for bringing the system into
core from a Q disc. For more information concerning this
disc see AP7201 (Drum Appendix).
~S1~L2. Interfaces~
Other modules used~
   None~
Ideal hardware registers used~
   None~
Q hardware registers used~
   (AP7 name)              (MC name)~
   V.DISC.DATA~
   V.DISC.CS~
Interrupt procedures~
   None~
Interface procedures~
   BOOT.SYS(VERSION,DRIVE,DISC)~
Interface variables~
   None~
Configurations parameters~
   None~
~S1~L2.1 MUSS Interface
~S1~L2.1.1 Hardware Interface
~BNone
~S1~L2.1.2 Software Interface
~B1) BOOT.SYS(VERSION,DRIVE,DISC).
~BThis procedure is responsible for booting in the system, switching
from real to virtual memory mode and entering the system initialisation
code. (It is called from the initial bootstrap (see AP7001).
~S1~L2.2 Q interface
~BSee AP7021.
~S1~L3. Implementation~
~S1~L3.1 Outline of Operation~
~BThe operation of this module is obvious from the flowcharts.
~S1~L3.2 Data Structures~
~
None.
~S1~L3.3 Special Notes
~BNone~
~Y
~P
~V9 -1
~D15
~HFLOWCHARTS
~
~
~H                AP7211
~V9 -1
~F
@TITLE AP721(1,9)

@COL 1S-2R-3R-4R-5R-6F
@FLOW 1-2-3-4-5-6
@BOX 1.0
SYSTEM BOOTSTRAP
@BOX 4.0
PROCEDURES IN MODULE:
   1 BOOT SYS
   2 COPY BOOTSTRAP
   3 READ SYSTEM
   4 DISC READ
@BOX 6.0
END
@BOX 1.1
MODULE BOOTSTRAP (BOOT.SYS);
@BOX 3.1
LITERAL / LOGICAL READY = %80, BOOT.SIZE = %1000, PORT = 0, MAX.TRANSFER.SIZE =
32;
*VTYPE LOGICAL;
VSTORE V.PAR [1024] %8004;
VSTORE V.MU6G.EXTENSION %48004;
VSTORE V.UNIBUS.EXTENSION %4800C;
VSTORE V.SI.CONTROL %4F704;
VSTORE V.SI.COUNT %4F70C;
VSTORE V.SI.CYL %4F714;
VSTORE V.SI.TRACK %4F71C;
VSTORE V.SI.CADDR %4F724;
VSTORE V.SI.ERROR %4F72C;
VSTORE V.SI.SEEK.STATUS %4F734;
VSTORE V.SI.SEEK.ADDR %4F73C;
VSTORE V.SI.DATA.BUFFER %4F744;
VSTORE V.SI.COMMS %4F74C;
VSTORE V.SI.SC %4F754;
VSTORE V.I.STATUS %74;
VSTORE V.O.STATUS %6C;
VSTORE V.BUFFER %64;
@BOX 4.1
PSPEC BOOT.SYS (INTEGER);
PSPEC CONS.OUT.CH (INTEGER);
PSPEC READ.DISC (ADDR, ADDR, LOGICAL);
PSPEC READ.SYSTEM (INTEGER);
   #AP721.1
   #AP721.5
   #AP721.4
   #AP721.3
@BOX 6.1
*END
@END
@TITLE AP721.1(1,9)

@COL 1S-2R-8R-3R-6R-4R-5F
@FLOW 1-2-8-3-6-4-5
@BOX 1.0
BOOT SYSTEM (VERSION, DRIVE, DISC)
@BOX 2.0
COPY BOOTSTRAP TO TOP OF STORE
@BOX 3.0
READ SYSTEM IN FROM DISC
@BOX 4.0
JUMP TO INITIALIZATION CODE
@BOX 5.0
END
@BOX 6.0
SET UP PARS FOR TEMPORARY
REAL STORE ACCESS AND MMU SEG
@BOX 7.0
SET UP REST OF LOCKED PARS
@BOX 8.0
CLEAR STORE UP TO BOOTSTRAP
@BOX 1.1
PROC BOOT.SYS (VERSION);
INTEGER I, J, K, PAR.NO, NO.OF.PARS;
LOGICAL PAR.ENTRY;
ADDR [LOGICAL] STORE;
DATAVEC INIT.ADDR (LOGICAL)
   %11200000
END
PSPEC COPY.BOOTSTRAP ();
#AP721.1.1
@BOX 2.1
COPY.BOOTSTRAP ();
@BOX 3.1
READ.SYSTEM (VERSION);
@BOX 4.1
*#%C483; :: JMP 3/4
:: -> START OF INITIALIZATION CODE
@BOX 5.1
END
@BOX 6.1
:: SETUP PARS
DATAVEC V.ADDRS (LOGICAL8)
   ::SEG.NO   ACCESS
       %82       %50
       %83       %60
       %85       %60
       %81       %60
       %89       %50
END
DATAVEC SIZES (INTEGER)
   16 32 1 8 2
END
*#%243F; :: LDM-1 #1
*#%21C4 %011D; :: STM1 @%11D/1 PURGE CPRS
*#%21C4 %011E; :: STM1 @%11E/1 PURGE CACHE
*#%21C4 %011F; :: STM1 @%11F/1 RESET PARS
*#%2400;
*#%21C4 %0100;
%200 * %62 ! %50 => V.PAR [%62] + %200 => V.PAR [%63]; :: SET PAR FOR BOOT CODE
%200 * %80 ! %60 => V.PAR [%80] + %200 => V.PAR [%81]; :: SET PAR FOR STACK
-1 => I => PAR.NO;
FOR K < SIZE (^SIZES) DO
   SIZES [K] => NO.OF.PARS;
   V.ADDRS [1 +> I] <<- 16 ! V.ADDRS [1 +> I] => PAR.ENTRY;
   FOR J < NO.OF.PARS DO
      PAR.ENTRY => V.PAR [1 +> PAR.NO];
      %200 +> PAR.ENTRY;
   OD
OD
MAKE (LOGICAL, 1, %8000) => STORE;
VERSION - 1 => STORE^ [0];
INIT.ADDR [0] => I;
*#%2404; ::LDM1 #4
*#%21C4 %0101; ::STM1 @%101/1;
@BOX 8.1
:: CLEAR STORE
MAKE (LOGICAL, %C000, 0) => STORE;
FOR I < %C000 DO
   0 => STORE^ [I];
OD
@END

@TITLE AP721.1.1(1,9)

@COL 1S-2R-3R-4F
@FLOW 1-2-3-4
@BOX 1.0
COPY BOOTSTRAP
@BOX 2.0
COPY BOOTSTRAP TO TOP OF STORE
@BOX 3.0
SET STACKED PC TO NEW POSITION
@BOX 4.0
END
@BOX 1.1
PROC COPY.BOOTSTRAP;
INTEGER I;
ADDR [LOGICAL] HIGH, LOW;
@BOX 2.1
MAKE (LOGICAL, BOOT.SIZE, 0) => LOW;
MAKE (LOGICAL, BOOT.SIZE, %30000) => HIGH;
FOR I < BOOT.SIZE DO
   LOW^ [I] => HIGH^ [I];
OD
@BOX 3.1
*#%2481; :: LDM1 1/4
*#%4418; :: LDM2 #%18
*#%5D00 %FFF0; :: SFT2 #-16
*#%3052; :: ADD1 BM2
*#%2081; :: STM1 1/4
@BOX 4.1
END
@END
@TITLE AP721.3(1,9)

@COL 1S-2R-3R-5F
@FLOW 1-2-3-5
@BOX 1.0
READ SYSTEM (VERSION)
@BOX 2.0
INITIALIZE POINTERS
@BOX 3.0
READ IN SYSTEM
@BOX 4.0
SET VERSION AND DISC NUMBERS
@BOX 5.0
END
@BOX 1.1
PROC READ.SYSTEM (VERSION);
INTEGER SECTOR.SHIFT, I, T.SIZE, SCALE;
ADDR C.ADDR, D.ADDR;
ADDR [LOGICAL] TRAN.SIZE;
ADDR [ADDR] CORE.ADDR, DISC.ADDR;
DATAVEC V1.DISC.ADDR (ADDR)
   640 896 1824 1664
END
DATAVEC V1.TRAN.SIZE (LOGICAL)
   64 128 32 8
END
DATAVEC V1.CORE.ADDR (ADDR)
   %0 %8000 %18800 %1C800
END
DATAVEC V2.DISC.ADDR (ADDR)
   4640 4896 5824 5664
END
DATAVEC V2.TRAN.SIZE (LOGICAL)
   64 128 32 8
END
DATAVEC V2.CORE.ADDR (ADDR)
   %0 %8000 %18800 %1C800
END
@BOX 2.1
IF VERSION = 1 THEN
   ^V1.DISC.ADDR => DISC.ADDR;
   ^V1.TRAN.SIZE => TRAN.SIZE;
   ^V1.CORE.ADDR => CORE.ADDR;
ELSE
   ^V2.DISC.ADDR => DISC.ADDR;
   ^V2.TRAN.SIZE => TRAN.SIZE;
   ^V2.CORE.ADDR => CORE.ADDR;
FI
@BOX 3.1
FOR I < SIZE (DISC.ADDR) DO
   DISC.ADDR^ [I] => D.ADDR;
   CORE.ADDR^  [I] => C.ADDR;
   TRAN.SIZE^ [I] => T.SIZE;
   WHILE T.SIZE > MAX.TRANSFER.SIZE DO
      READ.DISC (D.ADDR, C.ADDR, MAX.TRANSFER.SIZE);
      MAX.TRANSFER.SIZE -> T.SIZE;
      MAX.TRANSFER.SIZE +> D.ADDR;
      MAX.TRANSFER.SIZE <<- 9 +> C.ADDR;
   OD
   READ.DISC (D.ADDR, C.ADDR, T.SIZE);
OD
@BOX 5.1
END
@END
@TITLE AP721.4(1,9)

@COL 1S-2R-3R-4R-5R-6R-7R-8F

@FLOW 1-2-3-4-5-6-7-8

@BOX 1.1
PROC READ.DISC (SECTOR, C.ADDR, TRAN.SIZE);
INTEGER CYL, TRACK;
@BOX 2.1
%3F => V.UNIBUS.EXTENSION;
1 => V.SI.SC;
WHILE V.SI.SC & %80 = 0 DO OD;
@BOX 3.1
WHILE V.SI.SEEK.STATUS & 7 = 1 DO OD;
WHILE V.SI.SEEK.STATUS & 7 /= 0 DO
   1 => V.SI.CONTROL;
OD
@BOX 4.1
SECTOR / 608 => CYL ! PORT => V.SI.CYL;
CYL * 608 -: SECTOR => V.SI.TRACK;
256 * TRAN.SIZE => V.SI.COUNT;
@BOX 5.1
C.ADDR => V.SI.CADDR;
C.ADDR ->> 15 => V.MU6G.EXTENSION;
@BOX 6.1
5 => V.SI.CONTROL;
@BOX 7.1
WHILE V.SI.CONTROL & %80 = 0 DO OD;
0 => V.SI.SC;
@BOX 8.1
END
@END
@TITLE AP721.5(1,9)

@COL 1S-2R-3F

@FLOW 1-2-3

@BOX 1.1
PROC CONS.OUT.CH (CH);
@BOX 2.1
0 => V.I.STATUS;
WHILE V.O.STATUS = 1 DO OD
CH => V.BUFFER;
@BOX 3.1
END
@END

