@X @~
~V7 56 2 -5
~D10
~H                    MUSS
~
~
~D10
~H             AP7012
~D10
~MMANCHESTER UNIVERSITY  -  CONFIDENTIAL
~
~
                                                            ISSUE 11~
~V9 -1
~P
~V9 1
~YAP7012
~S~M~OAP7 IMPLEMENTATION DESCRIPTION
~S~M~OSection 1 Version 2
~S~OSection 1.2 PDP/11 Processor Appendix
~S~O1. General Description
~BThe PDP/11 Processor Appendix contains the procedures necessary to map those
features of the ideal machine needed in the MU6 front-end processor
onto the PDP11.  It is thus a subset of the procedures necessary for
a PDP11 when used as a full MUSS machine.
~S~O2. Interfaces
~
Other modules used:~
   SYS01   Co-ordinator~
~
Ideal hardware registers used:~
   V.HW.INTS~
   V.SW.INTS~
   V.HALT.MASK~
   V.FI~
   V.CALL.LINK~
   V.EXIT.LINK~
   V.PURGE.CACHE~
~
Interrupt procedures:~
   PDP11.APPENDIX.INT~
~
Interface procedures:~
   SET.HW.INT(ACTIVITY)~
   CLEAR.HW.INT(ACTIVITY)~
   MS.BIT(WORD)~
   BIT(INDEX)~
   SET.BIT(VEC,INDEX)~
   CLEAR.BIT(VEC,INDEX)~
   TEST.BIT(VEC,INDEX)~
~
Configuration parameters:~
   None~
~
Machine functions:~
   ALLOW.INTERRUPTS~
   INHIBIT.INTERRUPTS~
~S~O2.1 Hardware Interface
~BThe ideal hardware registers are described in SYS01, co-ordinator
module.
~S~O2.2 Software Interface
~S11) SET.HW.INT(ACTIVITY)
~BThis procedure sets the appropriate bit in V.HW.INT and updates
the interrupt tree.
~S12) CLEAR.HW.INT(ACTIVITIES)
~BThis procedure clears the appropriate bit in V.HW.INT and updates
the interrupt tree.
~S13) MS.BIT(WORD)
~BThis procedure finds and returns the most significant bit in WORD,
which must be non-zero.
~S14) BIT(INDEX)
~BThis procedure returns a bit pattern with the required bit set.
~S15) SET.BIT(VEC,INDEX)
~BThis procedure sets the indicated bit in the specified bit vector.
~S16) CLEAR.BIT(VEC,INDEX)
~BThis procedure clears the indicated bit in the specified bit vector.
~S17) TEST.BIT(VEC,INDEX)
~BThis procedure returns the value of the indicated bit in the
specified bit vector.
~S~O2.3 Machine Functions
~S11) ALLOW.INTERRUPTS
~BThis function sets the interrupt priority to the lowest level (0).
~S12) INHIBIT.INTERRUPTS
~BThis function sets the interrupt priority to the highest level (7).
~S~O2.4 Servicing of Interrupts
~BThe servicing of interrupts may be performed at one of three levels,
namely:~
~
~Mraw interrupt level
~Nappendix interrupt level
~NMUSS interrupt level.
~
The latter is the interrupt level state defined for the MUSS ideal
machine (as described in SYS000).
~BThe initial servicing of interrupts is controlled by the interrupt
vectors, which provide a jump into the corresponding raw interrupt level
code.  On entry to this code, the only context information saved is that
dumped on the stack by the hardware.  Any other registers required by the
raw interrupt level software must be preserved and restored within the
interrupt runtime.
~BThe raw interrupt level code is intended for the rapid servicing of
trivial interrupt conditions, such as the arrival of a single character
down a communication link.  To restrict the registers used by the
interrupt routine (and hence reduce the overheads of dumping and
restoring), this code is normally written in hexadecimal.
~BIf the interrupting condition requires more significant actions, then
appendix interrupt level should be entered.  Entry to this level is achieved
by stacking the parameter(s) necessary for the appendix level procedure and the
procedure
entry address, and then jumping into the system code at PDP11.APPENDIX.INT.
The entry sequence into the appendix level interrupt procedure saves the
full process context, and so these procedures may be written in
MUSL without needing to preserve or restore any registers explicitly.
~S~O3. Implementation
~S~O3.1 Outline of Operation
~BThe entry to Appendix interrupt level is provided by PDP11.APPENDIX.INT.
This label is exported by the module and is used by modules wishing
to enter Appendix interrupt level; to do so any necessary parameters are
stacked, followed by the starting address of the
procedure to be entered, and a jump to PDP11.APPENDIX.INT executed.
~BInitially the registers are saved in a special register dump area.
The required procedure is then called via the entry point on the stack.
On completion of the procedure the registers are restored
 and the interrupt servicing terminated.
~S~O3.2 Data Structures
~T# 12
~
BIT.POSN~IThis datavector is used in BIT.~
~
BIT.POSN8~IThis data vector is used in SET.BIT and TEST.BIT.~
~
BIT.MASK8~IThis data vector is used in CLEAR.BIT.~
~Y
~V9 -1
~P
~D15
~HFLOWCHARTS
~
~
~H             AP7012
~V9 -1
~F
@TITLE AP701(2,11)
@COL 1S-2R-3R-4R-5R-6F
@FLOW 1-2-3-4-5-6
@BOX 1.0
PDP11/10 PROCESSOR APPENDIX
@BOX 4.0
PROCEDURES IN MODULE:
   1 SET HW INT
   2 CLEAR HW INT
   3 INT TREE POST PROC
   4 PDP11 APPENDIX INT
   5 CALL LINK PRE PROC
   6 EXIT LINK POST PROC
   7 MS BIT
   8 BIT
   9 SET BIT
   10 CLEAR BIT
   11 TEST BIT
   12 INHIBIT INTERRUPTS PRE PROC
   13 ALLOW INTERRUPTS PRE PROC
   14 UPDATE IDLE TIME
   15 CLOCK INTERRUPT
   16 RAW CLOCK INT
@BOX 6.0
END
@BOX 1.1
#AP701/1
MODULE (V.HW.INTS, V.SW.INTS, V.HALT.MASK, V.FI,
   SET.HW.INT, CLEAR.HW.INT, UPDATE.IDLE.TIME,
   V.CALL.LINK, V.EXIT.LINK, V.PURGE.CACHE,
   INHIBIT.INTERRUPTS, ALLOW.INTERRUPTS,
   MS.BIT, BIT, SET.BIT, CLEAR.BIT, TEST.BIT, PDP11.APPENDIX.INT);
@BOX 2.1
@BOX 3.1
*GLOBAL 5;
#AP701/2
@BOX 4.1
*CODE 2;
PSPEC SET.HW.INT (LOGICAL);
PSPEC CLEAR.HW.INT (LOGICAL);
::PSPEC INT.TREE.POST.PROC ();
:: PSPEC CALL.LINK.PRE.PROC ();
:: PSPEC EXIT.LINK.POST.PROC ();
PSPEC MS.BIT (LOGICAL) / INTEGER;
PSPEC BIT (INTEGER) / LOGICAL;
PSPEC SET.BIT (ADDR [LOGICAL8], INTEGER);
PSPEC CLEAR.BIT (ADDR [LOGICAL8], INTEGER);
PSPEC TEST.BIT (ADDR [LOGICAL8], INTEGER) / INTEGER;
::PSPEC INHIBIT.INTERRUPTS.PRE.PROC ();
::PSPEC ALLOW.INTERRUPTS.PRE.PROC ();
PSPEC UPDATE.IDLE.TIME ();
PSPEC DL11.CLOCK.INT ();
::RAW INTERRUPT ENTRY
   #AP701.1
   #AP701.2
   #AP701.3
   #AP701.4
   #AP701.5
   #AP701.6
   #AP701.7
   #AP701.8
   #AP701.9
   #AP701.10
   #AP701.11
   #AP701.14
   #AP701.15
   #AP701.16
@BOX 5.1
*CODE 7;
BEGIN
VSTORE INT.STORE [%100] %0;
VSTORE RAW.INT.PTR %23E;
TYPE PROC.ADDR.TYPE IS
   ADDR DL11.CLOCK.INT P
OR
   LOGICAL16 PROC.ADDRESS;
PROC.ADDR.TYPE PROC.ADDR;
^DL11.CLOCK.INT => P OF PROC.ADDR;
PROC.ADDRESS OF PROC.ADDR => RAW.INT.PTR;
RAW.CLOCK.INT => INT.STORE [%20];
%E0 => INT.STORE [%21];
::START CLOCK
%40 => V.DL11.CLOCK.STATUS;
1 => AT.INT.LEVEL;
END
@BOX 6.1
*END
@END
@TITLE AP701/1(2,11)
@COL 1S-2R-3R-4R
@FLOW 1-2-3-4
@BOX 1.0
OTHER MODULES REFERENCED
@BOX 1.1
:: EXTERNAL ENVIRONMENT
@BOX 2.1
@BOX 3.1
PSPEC POLL.DEVICES ();
@BOX 4.1
IMPORT LITERAL SYS01.INT.ACTIVITIES;
@END
@TITLE AP701/2(2,11)

@COL 1S

@BOX 1.0
DECLARATIONS
@BOX 1.1
LOGICAL VV.HW.INTS, VV.SW.INTS, VV.HALT.MASK, VV.FI, VV.PURGE.CACHE;
LOGICAL VV.INHIBIT.INTS, VV.ALLOW.INTS, INT.PENDING, AT.INT.LEVEL, TICKER;
VSTORE V.HW.INTS VV.HW.INTS;
VSTORE V.SW.INTS VV.SW.INTS > INT.TREE.POST.PROC.1;
VSTORE V.HALT.MASK VV.HALT.MASK > INT.TREE.POST.PROC.2;
VSTORE V.FI VV.FI;
VSTORE V.PURGE.CACHE VV.PURGE.CACHE;
*VTYPE ADDR;
VSTORE V.CALL.LINK %226 < CALL.LINK.PRE.PROC;
VSTORE V.EXIT.LINK %226 > EXIT.LINK.POST.PROC;
VSTORE V.SF %0 ::;
*VTYPE LOGICAL;
VSTORE INHIBIT.INTERRUPTS VV.INHIBIT.INTS ;
VSTORE ALLOW.INTERRUPTS VV.ALLOW.INTS ;
VSTORE V.DL11.CLOCK.STATUS %FF66;
DATAVEC BIT.POSN (LOGICAL)
   %8000 %4000 %2000 %1000
   %0800 %0400 %0200 %0100
   %0080 %0040 %0020 %0010
   %0008 %0004 %0002 %0001
END
DATAVEC BIT.POSN8 (LOGICAL8)
   %80 %40 %20 %10
   %08 %04 %02 %01
END
DATAVEC BIT.MASK8 (LOGICAL8)
   %7F %BF %DF %EF
   %F7 %FB %FD %FE
END
@END
@TITLE AP701.1(2,11)
@COL 1S-2R-3R-4F
@FLOW 1-2-3-4
@BOX 1.0
SET HW INT (ACTIVITY)
@BOX 2.0
SET APPROPRIATE BIT
IN V HW INTS
@BOX 3.0
UPDATE INTERRUPT TREE
@BOX 4.0
END
@BOX 1.1
PROC SET.HW.INT (ACTIVITY);
@BOX 2.1
ACTIVITY !> VV.HW.INTS;
@BOX 3.1
VV.HW.INTS ! VV.SW.INTS ! VV.HALT.MASK -= VV.HALT.MASK => VV.FI;
IF AT.INT.LEVEL = 0 AND VV.FI & SYS01.INT.ACTIVITIES /= 0 THEN
   1 => INT.PENDING;
FI
@BOX 4.1
END
@END
@TITLE AP701.2(2,11)
@COL 1S-2R-3R-4F
@FLOW 1-2-3-4
@BOX 1.0
CLEAR HW INT (ACTIVITY)
@BOX 2.0
CLEAR APPROPRIATE BIT
IN V HW INTS
@BOX 3.0
UPDATE INTERRUPT TREE
@BOX 4.0
END
@BOX 1.1
PROC CLEAR.HW.INT (ACTIVITY);
@BOX 2.1
ACTIVITY & VV.HW.INTS -=> VV.HW.INTS;
@BOX 3.1
VV.HW.INTS ! VV.SW.INTS ! VV.HALT.MASK -= VV.HALT.MASK => VV.FI;
@BOX 4.1
END
@END
@TITLE AP701.3(2,11)
@COL 1S-3R
@FLOW 1-3
@BOX 1.0
INT TREE POST PROC
@BOX 3.0
UPDATE INTERRUPT TREE
@BOX 1.1
::INT TREE POST PROC 1 FOR V.SW.INTS
::INT TREE POST PROC 2 FOR V.HALT.MASK
@BOX 3.1
PROC INT.TREE.POST.PROC.1;
   *#%15DF %00E0 %FFFE; ::INHIBIT INTS;
   VV.HW.INTS ! VV.SW.INTS ! VV.HALT.MASK -= VV.HALT.MASK => VV.FI;
   *#%15DF %0000 %FFFE; ::ALLOW INTS;
END

PROC INT.TREE.POST.PROC.2;
   *#%15DF %00E0 %FFFE; ::INHIBIT INTS;
   VV.HW.INTS ! VV.SW.INTS ! VV.HALT.MASK -= VV.HALT.MASK => VV.FI;
   *#%15DF %0000 %FFFE; ::ALLOW INTS;
END
@END
@TITLE AP701.4(2,11)
@COL 1S-2R-3R-4R-5F
@FLOW 1-2-3-4-5
@BOX 1.0
PDP11 APPENDIX INTERRUPT
@BOX 2.0
SAVE REGISTERS
@BOX 3.0
CALL PROCEDURE
@BOX 4.0
RESTORE REGISTERS AND
RETURN FROM INTERRUPT
@BOX 5.0
END
@BOX 1.1
PDP11.APPENDIX.INT: BEGIN
@BOX 2.1
*#%119F %210 ::MOV SP,@#%210;
*#%15C6 %210 ::MOV #%210,SP;
*#%1166  ::MOV R5,-(SP);
*#%1126  ::MOV R4,-(SP);
*#%10E6  ::MOV R3,-(SP);
*#%10A6  ::MOV R2,-(SP);
*#%1066  ::MOV R1,-(SP);
*#%1026  ::MOV R0,-(SP);
*#%17C6 %210 ::MOV @#%210,SP;
@BOX 3.1
*#%09DE  ::JSR PC,@(SP)+;
@BOX 4.1
*#%119F %210 ::MOV SP,@#%210;
*#%15C6 %210 ::MOV #%210,SP;
*#%E5C6 %000C ::SUB #12,SP;
*#%1580 :: RESTORE REGS
*#%1581;
*#%1582;
*#%1583;
*#%1584;
*#%1585;
*#%1386  ::MOV (SP),SP;
*#%0002 :: RTI
@BOX 5.1
END
@END
@TITLE AP701.5(2,11)
@COL 1S-2R-3F
@FLOW 1-2-3
@BOX 1.0
CALL LINK PRE PROC
@BOX 2.0
RETURN STACK POINTER
@BOX 3.0
END
@BOX 1.1
PROC CALL.LINK.PRE.PROC;
@BOX 2.1
*#%115F %226 ::SAVE R5
*#%15DF %0000 %FFFE::ALLOW INTERRUPTS;
@BOX 3.1
END
@END


@TITLE AP701.6(2,11)
@COL 1S-2R-3F
@FLOW 1-2
@BOX 1.0
EXIT LINK POST PROC
@BOX 2.0
RESET STACK POINTER
AND EXIT VIA LINK ON STACK
@BOX 3.0
END
@BOX 1.1
PROC EXIT.LINK.POST.PROC;
@BOX 2.1
*#%15DF %00E0 %FFFE::INHIBIT INTERRUPTS;
*#%17C5 %226 ::RELOAD R5;
@BOX 3.1
END
@END


@TITLE AP701.7(2,11)
@COL 1S-2R-3F
@FLOW 1-2-3
@BOX 1.0
MS BIT
@BOX 2.0
FIND MOST SIGNIFICANT
BIT IN WORD
@BOX 3.0
END
@BOX 1.1
PROC MS.BIT (WORD);
@BOX 2.1
0 => MS.BIT;
WHILE WORD & %8000 = 0 DO
   WORD <<- 1 => WORD;
   1 +> MS.BIT;
OD
@BOX 3.1
END
@END


@TITLE AP701.8(2,11)
@COL 1S-2R-3F
@FLOW 1-2-3
@BOX 1.0
BIT
@BOX 2.0
RETURN BIT PATTERN WITH
REQUIRED BIT SET
@BOX 3.0
END
@BOX 1.1
PROC BIT (INDEX);
@BOX 2.1
BIT.POSN [INDEX] => BIT;
@BOX 3.1
END
@END

@TITLE AP701.9(2,11)
@COL 1S-2R-3F
@FLOW 1-2-3
@BOX 1.0
SET BIT
@BOX 2.0
SET BIT IN SPECIFIED
BIT VECTOR
@BOX 3.0
END
@BOX 1.1
PROC SET.BIT (VEC, INDEX);
@BOX 2.1
BIT.POSN8 [INDEX & 7] !> VEC^ [INDEX / 8];
@BOX 3.1
END
@END

@TITLE AP701.10(2,11)
@COL 1S-2R-3F
@FLOW 1-2-3
@BOX 1.0
CLEAR BIT
@BOX 2.0
CLEAR BIT IN SPECIFIED
BIT VECTOR
@BOX 3.0
END
@BOX 1.1
PROC CLEAR.BIT (VEC, INDEX);
@BOX 2.1
BIT.MASK8 [INDEX & 7] &> VEC^ [INDEX / 8];
@BOX 3.1
END
@END


@TITLE AP701.11(2,11)
@COL 1S-2R-3F
@FLOW 1-2-3
@BOX 1.0
TEST BIT
@BOX 2.0
FIND VALUE OF SPECIFIED BIT
IN BIT VECTOR
@BOX 3.0
END
@BOX 1.1
PROC TEST.BIT (VEC, INDEX);
@BOX 2.1
BIT.POSN8 [INDEX & 7] & VEC^ [INDEX / 8] => TEST.BIT;
@BOX 3.1
END
@END


@TITLE AP701.12(2,11)

@COL 1S-2R-3F

@FLOW 1-2-3

@BOX 1.0
INHIBIT INTERRUPTS PRE PROC
@BOX 2.0
INHIBIT INTERRUPTS
@BOX 3.0
END
@BOX 1.1
PROC INHIBIT.INTERRUPTS.PRE.PROC;
@BOX 2.1
*#%15DF;
*#%00E0;
*#%FFFE;
@BOX 3.1
END
@END


@TITLE AP701.13(2,11)

@COL 1S-2R-3F

@FLOW 1-2-3

@BOX 1.0
ALLOW INTERRUPTS PRE PROC
@BOX 2.0
ALLOW INTERRUPTS
@BOX 3.0
END
@BOX 1.1
PROC ALLOW.INTERRUPTS.PRE.PROC;
@BOX 2.1
*#%15DF;
*#%0000;
*#%FFFE;
@BOX 3.1
END
@END
@TITLE AP701.14(2,11)
@COL 1S-2F
@FLOW 1-2
@BOX 1.0
UPDATE IDLE TIME
@BOX 2.0
END
@BOX 1.1
PROC UPDATE.IDLE.TIME;
@BOX 2.1
END
@END


@TITLE AP701.15(2,11)
@COL 1S-2R-3R-4F
@FLOW 1-2-3-4
@BOX 1.0
DL11 CLOCK INTERRUPT PROC
@BOX 2.0
RESTART CLOCK
@BOX 3.0
POLL I/O DEVICES
@BOX 4.0
END
@BOX 1.1
PROC DL11.CLOCK.INT;
@BOX 2.1
%40 => V.DL11.CLOCK.STATUS;
@BOX 3.1
IF 1 -> TICKER =< 0 THEN
   50 => TICKER;
   POLL.DEVICES ();
FI
@BOX 4.1
END
@END

@TITLE AP701.16(2,11)
@COL 1R
@BOX 1.0
RAW INTERRUPT ENTRY CODE
@BOX 1.1
RAW.CLOCK.INT:
*#%17E6 %023E ::MOV PROC.ADDR,-(SP);
-> PDP11.APPENDIX.INT;
@END
