@X @~
~L3 COUK1247
80
~V7 56 2 -5
~D10
~H                    MUSS
~
~
~D10
~H            AP5024
~D10
~MMANCHESTER UNIVERSITY  -  CONFIDENTIAL~
~
~
                                                             ISSUE 11~
~V9 -1
~P
~V9 1
~YAP5024
~S1~M~OAP5 IMPLEMENTATION DESCRIPTION~
~S1~M~OSection 2  Version 4~
~S1~OSection 2.1 Drum Appendix (DMA-PTV)~
~S1~O1. General Description~
~BThis module is concerned with driving the 'drum'
described in SYS Section 3 (Drum Manager). The 'drum' in this
instance is a
SMS FWT50000 Floppy/Fixed Disc Storage System.
The SMS controller is in turn accessed via the PTV DMA controller
as described in Section 4.
~S1~O2. Interfaces~
~3
~
Other modules used~
   SYS Section 1 (Coordinator)~
   SYS Section 12 (System Error)~
   SYS Section 14 (Virtual Store Manager)~
Ideal hardware registers used~
   V.DISC.CONTROL~
   V.DISC.SIZE~
   V.DISC.C.ADDRESS~
   V.DISC.D.ADDRESS~
Q hardware registers used~
   (AP5 name)             (Description)~
   V.DISC.DATA             SASI data register~
   V.DISC.CS               SASI control register~
   V.DMAC.CSR              Channel status register~
   V.DMAC.DCR              Device control register~
   V.DMAC.OCR              Operation control register~
   V.DMAC.SCR              Sequence control register~
   V.DMAC.CCR              Channel control register~
   V.DMAC.NIV              Normal interrupt vector~
   V.DMAC.EIV              Error  interrupt vector~
   V.DMAC.MTC              Memory transfer counter~
   V.DMAC.MAR              Memory address register~
Interrupt procedures~
   Q.DISC.INT (DUMMY)~
Interface procedures~
   None~
Interface variables~
   None~
Configuration parameters~
   None~
~0
~S1~O2.1 MUSS Interface~
~S1~O2.1.1 Hardware Interface~
~BThe ideal hardware registers are
described in SYS Section 3.~
~S1~O2.1.2 Software Interface~
~S11) Q.DISC.INT (DUMMY)~
~BThis procedure services Q interrupts
and is called by the DMA interrupt
processing code when a DMA disc interrupt
is detected.~
~S1~O2.2 Q Interface~
~BSee SMS FWT50000 Manual.~


~S1~O3. Implementation~
~S1~O3.1 Outline of Implementation~
~BThe following procedures are private to this module.
~S11) DISC.CONTROL.POST.PROC~
~BThis procedure translates ideal
drum commands into Q commands.~
~S12) START.TRANSFER ()~
~BThis procedure evaluates the drum
and core addresses and initiates the transfer.~
~S1~O3.2 Data Structures~
~T%37
~
~
MAX.BYTE.XFER~IA literal giving the maximum transfer size in bytes.~
~
SECTOR.SHIFT~IAn integer 'constant' giving the sector size log}2{.~
~
SCALE~IAn integer 'constant' giving the page size / sector size ratio log}2{.~
~
MAX.SECTOR.XFER~IAn integer 'constant' giving the maximum transfer
size in sectors.~
~
DISC.STATUS~IA logical variable giving the status of the disc
as follows,~
~I0 = IDLE, 1 IN TRANSFER.~
~
DIRN~IAn integer variable giving the direction of the
transfer as follows~
~I1 = READ, 2 = WRITE.~
~
AMOUNT~IAn integer variale giving the size of the
current transfer in bytes.~
~
TRAN.SIZE~IA logical variable giving the size of the
current transfer in sectors.~
~
D.SIZE~IA logical variable giving the size of the
outstanding transfers in bytes.~
~
C.ADDR~IAn ADDR variable giving the
current core address of the transfer.~
~
D.ADDR~IAn ADDR variable giving the current
disc address of the transfer.~
~S1~O3.3 Special Notes~
~BThe information concerning the disc type (Logical
Unit No) and the drive number are passed to this Appendix
in the variables DISC.TYPE and DRIVE.NO which are initialised
by the system bootstrap using information received from the initial
bootstrap.
~BThe machine-dependent code used in
driving the 'drum' is contained in the
machine functions:~
~
~MINHIBIT.INTERRUPTS~
~NALLOW.INTERRUPTS~
~S1~O4. DMA-SASI Interface~
~BThe PTV/68000 DMA controller card is based on a HITACHI
type HD68450  DMAC chip, and is described in their target
specification. The chip is connected to the PTV system
bus and can be used to do memory to memory transfers or
memory to/from memory mapped peripheral transfers.
~BThe DMAC chip consists of four independent DMA channels.
Channel zero (0) is used to support a SASI interface as
described below.
~BSelection and control logic is provided which allows direct
communication between the system bus and the SASI port when
the port is selected. The SASI port is also selected when it is
implicitly addressed during DMA transfers.
~BDuring DMA data transfer, byte-word funnelling is done by
discrete sequential logic on the DMA card. This permits minimal
usage of the system bus.
~S1~O4.2 SASI PORT
~BThe SASI port can be directly addressed by the MPU.
Location 2840 (V.DISC.CS) provides access to the bits as
defined below. Location 2841 (V.DISC.DATA) provides access
to the data.
~BThe control byte (location 2840) is defined as follows:~
~3
~
     Bit 0  - Active high - DMA.MODE   - R/W~
         1  - Active high - INT.ENABLE - R/W~
         2  - Active high - SELECT     - R/W~
         3  - Active low  - MESSAGE    - R~
         4  - Active low  - CONTROL    - R~
         5  - Active low  - INPUT      - R~
         6  - Active low  - REQUEST    - R~
         7  - Active low  - BUSY       - R~
~0
~
Active high signals are asserted by a logical 1.~
Active low signals are asserted by a logical 0.~
~
    Bit 0: DMA.MODE:~
~
The DMA.MODE bit must be asserted to enable the byte-word
funnel and to enable handshaking between the SASI port and the DMAC.~
~
    Bit 1: INT.ENABLE:~
~
The INT.ENABLE bit causes a level 4 interrupt to be generated
when REQUEST is asserted by the SASI disc controller.~
~
    Bit 2-7:~
~
The SELECT,MESSAGE,CONTROL,INPUT,REQUEST, AND BUSY bits
conform to the SASI signal definitions.
~BThe SASI ACKNOWLEDGE signal will be generated automatically for
each REQUEST during DMA transfers. It will also be generated
in response to the REQUEST signal when data location 2841 (V.DISC.DATA)
is accessed by the MPU.
~BThe SASI RESET signal is connected to the system reset.
~S1~O4.2 DMA operation~
~BDMA transfer can only be used for the data transfer portion
of the SASI protocol. Selection, command, and status transfers must
be accomplished thru use of the SASI port.
~BTo cause DMA data transfer, the DMA.MODE bit is asserted and the
INT.ENABLE is negated. This sequence is, ofcourse, initiated only
after the DMA registers are initialized.
~BThe DMA registers should use the following initialization:
~
~BDevice Control Register: (DCR)~
~3
    XRM - Cycle steal mode (with or without hold)~
    DTYP- Device with ACK, implicitly addressed~
    DPS - 16-bit port~
    PCL - Abort on input~
~0
~BOperation Control Register: (OCR)~
~3
    DIR - as needed~
    SIZE- word operation~
    CHAIN-as needed~
    REQG- REQ line initiates an operand transfer~
~0
~BSequence Control Register: )OCR)~
~3
    MAC - as needed~
    DAC - as needed~
~0
~BChannel Control Register: (CCR)~
~3
    STR - as needed~
    CNT - as needed~
    HLT - as needed~
    SAB - as needed~
    INT - interrupts enabled~
~0
~BChannel Priority Register: (CPR)~
~3
    CP  - set to 0~
~0
~BInterrupt Vector Registers: (NIV,EIV)
    These are initialized to point to the index value of the
DISC interrupt handler (29).
~BErrors detected by the disc controller will cause it to
assert it's CONTROL signal before the DMAC asserts DONE.
This condition is detected and will cause the logic to assert
PCL to the DMAC. Assertion of PCL should cause the DMAC to
generate an interrupt.
~BThe DMA registers are mapped into locations 2900-29FF.
~BLevel 4 interrupts caused by the DMAC can be acknowledged
by reading location 2881. Reading this location causes the
return of the interrupt vector value.
~BThe DMA board generates parity for all address and data
outputs. When errors are detected, PCL is asserted and causes
the operation to be aborted.
~Y
~V9 -1
~P
~V9 -1
~D15
~HFLOWCHARTS
~
~
~H               AP5024
~V9 -1
~F
@X @~
~V7 56 2 -5
~D10
~H                    MUSS
~
~
~D10
~H            AP5025
~D10
~MMANCHESTER UNIVERSITY  -  CONFIDENTIAL~
~
~
~V2 -16
                                                                       ISSUE 10~
~V2 0
~V9 -1
~P
~V9 1
~YAP5025
~S1~M~LAP5 IMPLEMENTATION DESCRIPTION~
~S1~M~LSection 2  Version 5~
~S1~LSection 2.1 Drum Appendix (RTV/PTV)~
~S1~L1. General Description~
~BThis module is concerned with driving the 'drum'
described in SYS Section 3 (Drum Manager). The 'drum' in this
instance is a
SMS FWT50000 Floppy/Fixed Disc Storage System.
~S1~L2. Interfaces~
Other modules used~
   SYS Section 1 (Coordinator)~
   SYS Section 12 (System Error)~
   SYS Section 14 (Virtual Store Manager)~
Ideal hardware registers used~
   V.DISC.CONTROL~
   V.DISC.SIZE~
   V.DISC.C.ADDRESS~
   V.DISC.D.ADDRESS~
Q hardware registers used~
   (AP5 name)             (MC name)~
   V.DISC.DATA~
   V.DISC.CS~
Interrupt procedures~
   Q.DISC.INT (DUMMY)~
Interface procedures~
   None~
Interface variables~
   None~
Configuration parameters~
   None~
~P~S1~L2.1 MUSS Interface~
~S1~L2.1.1 Hardware Interface~
~BThe ideal hardware registers are
described in SYS Section 3.~
~S1~L2.1.2 Software Interface~
~S11) Q.DISC.INT (DUMMY)~
~BThis procedure services Q interrupts
and is called by the system when such an
interrupt is detected.~
~S1~L2.2 Q Interface~
~BSee OMTI Handbook.~
~S1~LNote
~BThe register interface into the Q disc is arranged as follows~
~Q 4
~
~M~L5000         5001                    ~
~N~L|  Data Byte  | Control/Status Byte |~
~BThe Control/Status byte is arranged as follows~
~
- For Control (Write Operations)~
~Q 11
~
~M~L7     6              0~
~N~L|IE|SEL|          |  |~
~X{`
~N  |  |~
~N  |  |~
~N  |   -----{1 - set select line~
~N  |        {0 - clear select line~
~N  |~
~N   --------{1 - enable interrupts~
~N           {0 - disable interrupts~
~X{{
~
- For Status (Read Operations)~
~Q 3
~
~M~L  7   6   5   4   3      0 ~
~N~L|BSY|REQ|I/O|C/D|MSG|0|0|0|~
~BThe value of these bits correspond to the value of the
Signal lines with the same mnemonic.
~BHardware assistance in driving the Q disc is provided
in the following manner~
~
  -  BSY going high clears the select line~
  -  REQ going high generates an interrupt if IE is set~
  -  Reading or writing to the data byte clears the interrupt~
     and sets the ACK signal.~
  -  ACK is cleared when REQ from the controller clears.~
~S1~L3. Implementation~
~S1~L3.1 Outline of Implementation~
~BThe following procedures are private to this module.
~S11) DISC.CONTROL.POST.PROC~
~BThis procedure translates ideal
drum commands into Q commands.~
~S12) START.TRANSFER ()~
~BThis procedure evaluates the drum
and core addresses and initiates the transfer.~
~S1~L3.2 Data Structures~
~T%37
~
~
MAX.BYTE.XFER~IA literal giving the maximum transfer size in bytes.~
~
SECTOR.SHIFT~IAn integer 'constant' giving the sector size log}2{.~
~
SCALE~IAn integer 'constant' giving the page size / sector size ratio log}2{.~
~
MAX.SECTOR.XFER~IAn integer 'constant' giving the maximum transfer
size in sectors.~
~
DISC.STATUS~IA logical variable giving the status of the disc
as follows,~
~I0 = IDLE, 1 IN TRANSFER.~
~
DIRN~IAn integer variable giving the direction of the
transfer as follows~
~I1 = READ, 2 = WRITE.~
~
AMOUNT~IAn integer variale giving the size of the
current transfer in bytes.~
~
TRAN.SIZE~IA logical variable giving the size of the
current transfer in sectors.~
~
D.SIZE~IA logical variable giving the size of the
outstanding transfers in bytes.~
~
C.ADDR~IAn ADDR variable giving the
current core address of the transfer.~
~
D.ADDR~IAn ADDR variable giving the current
disc address of the transfer.~
~S1~L3.3 Special Notes~
~BThe information concerning the disc type (Logical
Unit No) and the drive number are passed to this Appendix
in the variables DISC.TYPE and DRIVE.NO which are initialised
by the system bootstrap using information received from the initial
bootstrap.
~BThe machine-dependent code used in
driving the 'drum' is contained in the
machine functions:~
~
~MINHIBIT.INTERRUPTS~
~NALLOW.INTERRUPTS~
~Y
~P
~V9 -1
~D15
~HFLOWCHARTS
~
~
~H               AP5022
~V9 -1
~F
@TITLE AP502(4,11)
@COL 1S-2R-3R-4R-5R-6F
@FLOW 1-2-3-4-5-6
@BOX 1.0
MC68000 (Q) DISC APPENDIX
@BOX 4.0
PROCEDURES IN MODULE:
   1 DISC CONTROL POST PROC
   2 DRUM CONTROL POST PROC
   3 Q DISC INT
   4 START TRANSFER
   5 ED POLL
@BOX 6.0
*END
@BOX 1.1
#AP502/1
MODULE (V.DISC.CONTROL, V.DISC.D.ADDRESS, V.DISC.C.ADDRESS, V.DISC.SIZE,
   V.DRUM.CONTROL, V.DRUM.D.ADDRESS, V.DRUM.C.ADDRESS, V.DRUM.SIZE,
   V.DRUM.SECTION, Q.DISC.INT, ED.POLL);
@BOX 2.1
TYPE DISC.VARS.TYPE IS
INTEGER SECTOR.SHIFT, MAX.SECTOR.XFER
INTEGER D.SIZE
LOGICAL DISC.STATUS
ADDR C.ADDR, D.ADDR, DRUM.OFFSET;
@BOX 3.1
*GLOBAL 5;
LITERAL / LOGICAL8 SEL = 4, BSY = %80, CTL.ID = 1, DMA = 1;
LITERAL / LOGICAL READ = 1, WRITE = 2;
LITERAL / LOGICAL32 MAX.BYTE.XFER = %8000;
LITERAL / LOGICAL8 BSY.CMD.REQ = %D0;
LOGICAL [SYS05.NO.OF.ED.UNITS] VV.DISC.CONTROL,
   VV.DISC.C.ADDRESS, VV.DISC.SIZE;
LOGICAL32 [SYS05.NO.OF.ED.UNITS]  VV.DISC.D.ADDRESS;
VSTORE V.DISC.CONTROL [SYS05.NO.OF.ED.UNITS] VV.DISC.CONTROL > DISC.CONTROL.POST
.PROC;
VSTORE V.DISC.D.ADDRESS [SYS05.NO.OF.ED.UNITS] VV.DISC.D.ADDRESS;
VSTORE V.DISC.C.ADDRESS [SYS05.NO.OF.ED.UNITS] VV.DISC.C.ADDRESS;
VSTORE V.DISC.SIZE [SYS05.NO.OF.ED.UNITS] VV.DISC.SIZE;
LOGICAL VV.DRUM.CONTROL, VV.DRUM.C.ADDRESS, VV.DRUM.SIZE, VV.DRUM.SECTION;
LOGICAL32  VV.DRUM.D.ADDRESS;
VSTORE V.DRUM.CONTROL VV.DRUM.CONTROL > DRUM.CONTROL.POST.PROC;
VSTORE V.DRUM.D.ADDRESS VV.DRUM.D.ADDRESS;
VSTORE V.DRUM.C.ADDRESS VV.DRUM.C.ADDRESS;
VSTORE V.DRUM.SIZE VV.DRUM.SIZE;
VSTORE V.DRUM.SECTION VV.DRUM.SECTION;
*VTYPE LOGICAL8;
VSTORE V.DISC.DATA %2841;
VSTORE V.DISC.CS   %2840;
VSTORE V.DMAC.CSR  %2900;
VSTORE V.DMAC.DCR  %2904;
VSTORE V.DMAC.OCR  %2905;
VSTORE V.DMAC.SCR  %2906;
VSTORE V.DMAC.CCR  %2907;
VSTORE V.DMAC.NIV  %2925;
VSTORE V.DMAC.EIV  %2927;
*VTYPE LOGICAL16;
VSTORE V.DMAC.MTC  %290A;
*VTYPE LOGICAL32;
VSTORE V.DMAC.MAR  %290C;
INTEGER DIRN, UNIT, HW.INT.COUNT, TRAN.UNIT;
LOGICAL32 AMOUNT;
LOGICAL TRAN.STATUS, TRAN.SIZE, POLL.WAIT;
DISC.VARS.TYPE [NO.OF.DISCS] DISC.VARS;
LOGICAL8 [SYS05.NO.OF.ED.UNITS] POLL.REQ;
DATAVEC DISC.SIZES (LOGICAL32)
   131040
   3968 [2]
   20448
END
@BOX 4.1
:: *CODE 2;
:: PSPEC DISC.CONTROL.POST.PROC ();
:: PSPEC DRUM.CONTROL.POST.PROC ();
:: *CODE 23;
PSPEC Q.DISC.INT (INTEGER);
PSPEC START.TRANSFER ();
PSPEC ED.POLL ();
*CODE 2;
   #AP502.1
   #AP502.2
*CODE 23;
   #AP502.3
   #AP502.4
   #AP502.5
@BOX 5.1
*CODE 7;
BEGIN
   FOR UNIT < NO.OF.DISCS DO
      SELECT DISC.VARS [UNIT];
      8 => SECTOR.SHIFT;
      MAX.BYTE.XFER ->> SECTOR.SHIFT => MAX.SECTOR.XFER;
      IF UNIT >= NO.OF.DRUM.SECTIONS THEN
         %8000 => VV.DISC.CONTROL [UNIT - NO.OF.DRUM.SECTIONS] => DISC.STATUS;
      ELSE
         OFFSET [UNIT] => DRUM.OFFSET;
      FI
      %AB=>V.DMAC.DCR;5=>V.DMAC.SCR;29=>V.DMAC.NIV=>V.DMAC.EIV;
   OD
END
@BOX 6.1
*END
@END
@TITLE AP502/1(4,11)
@COL 1S-2R-3R-4R
@FLOW 1-2-3-4
@BOX 1.0
OTHER MODULES REFERENCED
@BOX 4.0
SYS01 COORDINATOR
SYS03 DRUM MANAGER
SYS12 SYSTEM ERROR
SYS14 VIRTUAL STORE MANAGER
@BOX 1.1
:: EXTERNAL ENVIRONMENT
@BOX 2.1
IMPORT VSTORE LOGICAL ALLOW.INTERRUPTS, INHIBIT.INTERRUPTS;
IMPORT LITERAL ADDR REAL.STORE.ADDRESS;
IMPORT LITERAL NO.OF.DISCS, NO.OF.DISC.TYPES, SYS05.NO.OF.ED.UNITS,
   NO.OF.DRUM.SECTIONS;
INTEGER [NO.OF.DISCS] DISC.TYPE, DRIVE.NO, DEV.FM;
LOGICAL32 [NO.OF.DRUM.SECTIONS] OFFSET;
@BOX 3.1
PSPEC SET.HW.INT (LOGICAL);
PSPEC CLEAR.HW.INT (LOGICAL);
@BOX 4.1
IMPORT LITERAL LOGICAL SYS01.DRUM.ACTIVITY, SYS01.DISC.ACTIVITY;
PSPEC SYS12.SYSTEM.ERROR (INTEGER);
IMPORT LITERAL INTEGER SYS14.PAGE.SHIFT;
@END
@TITLE AP502.1(4,11)
@COL 1S-2R-3R-6R-7F
@FLOW 1-2-3-6-7
@BOX 1.0
DISC CONTROL POST PROC
@BOX 2.0
INHIBIT INTERRUPTS
@BOX 3.0
NOTE DISC COMMAND
@BOX 6.0
ALLOW INTERRUPTS
@BOX 7.0
END
@BOX 1.1
PROC DISC.CONTROL.POST.PROC;
PSPEC NOTE.DISC.COMMAND ();
#AP502.1.1
@BOX 2.1
VSUB => UNIT;
INHIBIT.INTERRUPTS;
@BOX 3.1
NOTE.DISC.COMMAND ();
@BOX 6.1
ALLOW.INTERRUPTS;
@BOX 7.1
END
@END
@TITLE AP502.1.1(4,11)
@COL 1S-3R-4T-5R-7F
@FLOW 1-3-4NO-5-7
@FLOW 4YES-7
@BOX 1.0
NOTE DISC COMMAND
@BOX 3.0
CLEAR HW INT
[AP501]
@BOX 4.0
COMMAND BITS CLEAR?
@BOX 5.0
START TRANSFER
[AP502.3]
@BOX 7.0
END
@BOX 1.1
PROC NOTE.DISC.COMMAND;
@BOX 3.1
SELECT DISC.VARS [UNIT + NO.OF.DRUM.SECTIONS];
IF DISC.STATUS & %F00 /= 0 AND
   1 -> HW.INT.COUNT = 0 THEN
   CLEAR.HW.INT (SYS01.DISC.ACTIVITY);
FI
@BOX 4.1
DISC.STATUS & %8000 ! VV.DISC.CONTROL [UNIT]
   => DISC.STATUS;
IF DISC.STATUS & 3 = 0
@BOX 5.1
VV.DISC.D.ADDRESS [UNIT] + 32 => D.ADDR;
VV.DISC.C.ADDRESS [UNIT] <<- SECTOR.SHIFT
   + REAL.STORE.ADDRESS => C.ADDR;
VV.DISC.SIZE [UNIT] => D.SIZE;
START.TRANSFER ();
@BOX 7.1
END
@END
@TITLE AP502.2(4,11)
@COL 1S-2R-3R-6R-7F
@FLOW 1-2-3-6-7
@BOX 1.0
DRUM CONTROL POST PROC
@BOX 2.0
INHIBIT INTERRUPTS
@BOX 3.0
NOTE DRUM COMMAND
@BOX 6.0
ALLOW INTERRUPTS
@BOX 7.0
END
@BOX 1.1
PROC DRUM.CONTROL.POST.PROC;
PSPEC NOTE.DRUM.COMMAND ();
#AP502.2.1
@BOX 2.1
INHIBIT.INTERRUPTS;
@BOX 3.1
NOTE.DRUM.COMMAND ();
@BOX 6.1
ALLOW.INTERRUPTS;
@BOX 7.1
END
@END
@TITLE AP502.2.1(4,11)
@COL 1S-3R-4T-5R-7F
@FLOW 1-3-4NO-5-7
@FLOW 4YES-7
@BOX 1.0
NOTE DRUM COMMAND
@BOX 3.0
CLEAR HW INT
[AP501]
@BOX 4.0
COMMAND BITS CLEAR?
@BOX 5.0
START TRANSFER
[AP502.3]
@BOX 7.0
END
@BOX 1.1
PROC NOTE.DRUM.COMMAND;
@BOX 3.1
SELECT DISC.VARS [VV.DRUM.SECTION];
CLEAR.HW.INT (SYS01.DRUM.ACTIVITY);
@BOX 4.1
DISC.STATUS & %8000 ! VV.DRUM.CONTROL
   => DISC.STATUS;
IF DISC.STATUS & 3 = 0
@BOX 5.1
VV.DRUM.D.ADDRESS + DRUM.OFFSET + 32 => D.ADDR;
VV.DRUM.C.ADDRESS <<- SECTOR.SHIFT
   + REAL.STORE.ADDRESS => C.ADDR;
VV.DRUM.SIZE => D.SIZE;
START.TRANSFER ();
@BOX 7.1
END
@END
@TITLE AP502.3(4,11)

@COL 1S-2T-17R-18R-19R-3T-4T-6N-5R-7F
@COL 9R-10N-11R-13R-14R-16N
@ROW 17-9
@ROW 3-10
@ROW 6-16
@FLOW 1-2NO-17-18-19-3NO-4NO-6-5-7
@FLOW 2YES-9-16
@FLOW 3YES-10-11-14
@FLOW 4YES-13-14-16-6
@BOX 1.0
Q DISC INT
@BOX 2.0
DISC INACTIVE?
@BOX 3.0
DISC IN ERROR?
@BOX 4.0
TRANSFER COMPLETE?
@BOX 5.0
START TRANSFER
[AP502.3]
@BOX 7.0
END
@BOX 9.0
HALT
@BOX 11.0
NOTE TRANSFER FAIL
@BOX 13.0
NOTE TRANSFER COMPLETE
@BOX 14.0
SET HW INT
[AP501]
@BOX 17.0
DISABLE INTERRUPTS
@BOX 18.0
TRANSFER DATA
@BOX 19.0
OBTAIN STATUS
@BOX 21.0
ERROR
@BOX 22.0
MARK STATUS FOR ERROR
@BOX 1.1
PROC Q.DISC.INT (DUMMY);
LOGICAL8 STATUS;
SELECT DISC.VARS [TRAN.UNIT];
@BOX 2.1
IF TRAN.STATUS = 0
@BOX 3.1
IF STATUS /= 0
@BOX 4.1
AMOUNT +> C.ADDR;
TRAN.SIZE +> D.ADDR;
TRAN.SIZE -> D.SIZE;
IF D.SIZE = 0
@BOX 5.1
0 => TRAN.STATUS;
START.TRANSFER ();
@BOX 7.1
END
@BOX 9.1
*#%60FE; :: BRA -2
@BOX 11.1
%200 !> DISC.STATUS;
@BOX 13.1
%100 !> DISC.STATUS;
@BOX 14.1
IF TRAN.UNIT < NO.OF.DRUM.SECTIONS THEN
   DISC.STATUS => VV.DRUM.CONTROL;
   SET.HW.INT (SYS01.DRUM.ACTIVITY);
ELSE
   DISC.STATUS => VV.DISC.CONTROL [TRAN.UNIT - NO.OF.DRUM.SECTIONS];
   IF 1 +> HW.INT.COUNT = 1 THEN
      SET.HW.INT (SYS01.DISC.ACTIVITY);
   FI
FI
@BOX 17.1
@BOX 18.1
*#%422E %FFFB       :: CLRB FFFB(A6) -CLEAR STATUS-
*#%74D0             :: MOVEQ #D0,D2
*#%227C %0000 %2840 :: MOVEL @V.DISC.CS,A1
*#%1638 %2900       :: MOVEB V.DMAC.CSR,D3
*#%0203 %0012       :: ANDI  D3,#%12
*#%1D43 %FFFB       :: MOVEB D3,FFFB(A6)
*#%11FC %F2 %2900   :: MOVEB #%F2,V.DMAC.CSR -CLEAR DMA-
@BOX 19.1
*#%4211            :: CLRB  (A1)  -CLEAR V.DISC.CS-
                   :: WAIT1:
*#%1611            :: MOVEB (A1),D3
*#%C602            :: AND   D2,D3
*#%66FA            :: BNZ   WAIT1
*#%1029 %0001      :: MOVEB 1(A1),D0
*#%0200 %0007      :: ANDIB %07,D0
*#%812E %FFFB      :: ORB   D0,FFFB(A6) -STATUS-
                   :: WAIT2:
*#%1611            :: MOVEB (A1),D3
*#%C602            :: AND   D2,D3
*#%66FA            :: BNZ   WAIT2
*#%1029 %0001      :: MOVEB 1(A1),D0
@END

@TITLE AP502.4(4,11)

@COL 1S-5T-10R-7T-2R-3R-8R-9R-6F

@FLOW 1-5NO-10-7FOUND-2-3-8-9-6
@FLOW 5YES-6
@FLOW 7NOT FOUND-6

@BOX 1.0
START TRANSFER
@BOX 2.0
INITIALIZE VARIABLES
FOR TRANSFER
@BOX 3.0
SET UP COMMAND BUFFER
@BOX 4.0
SET COMMAND
@BOX 5.0
TRANSFER IN PROGRESS?
@BOX 6.0
END
@BOX 7.0
SEARCH FOR OUTSTANDING TRANSFER
@BOX 8.0
SELECTION SEQUENCE
@BOX 9.0
COMMAND TRANSFER SEQUENCE
@BOX 10.0
POLL EXCHANGEABLE UNITS
#AP502.4.1
@BOX 1.1
PROC START.TRANSFER;
ADDR LOGICAL8 CORE;
INTEGER I;
LOGICAL8 [6] CMD.BUFFER;
@BOX 2.1
SELECT DISC.VARS [TRAN.UNIT];
1 => TRAN.STATUS;
IF D.SIZE > MAX.SECTOR.XFER THEN
   MAX.SECTOR.XFER => TRAN.SIZE;
   MAX.BYTE.XFER => AMOUNT;
ELSE
   D.SIZE => TRAN.SIZE <<- SECTOR.SHIFT => AMOUNT;
FI
@BOX 3.1
(IF DISC.STATUS & 3 => DIRN = READ THEN %18 ELSE %1A)
   => CMD.BUFFER [0];
DRIVE.NO [TRAN.UNIT] <<- 5 ! (D.ADDR ->> 16 & %1F) => CMD.BUFFER [1];
D.ADDR ->> 8 => CMD.BUFFER [2];
D.ADDR => CMD.BUFFER [3];
TRAN.SIZE => CMD.BUFFER [4];
DEV.FM [TRAN.UNIT] => CMD.BUFFER [5];
@BOX 5.1
IF TRAN.STATUS /= 0
@BOX 7.1
IF 1 +> TRAN.UNIT = NO.OF.DISCS THEN
   0 => TRAN.UNIT;
FI
-1 => I;
WHILE 1 +> I < NO.OF.DISCS AND
   DISC.STATUS OF DISC.VARS [TRAN.UNIT]
   & %8F03 /= 1 /= 2 DO
   IF 1 +> TRAN.UNIT = NO.OF.DISCS THEN
      0 => TRAN.UNIT;
   FI
OD
IF I = NO.OF.DISCS
@BOX 8.1
C.ADDR => V.DMAC.MAR;
AMOUNT->>1 => V.DMAC.MTC;
(IF DIRN=READ THEN %92 ELSE %12) => V.DMAC.OCR;
%88 => V.DMAC.CCR;
WHILE V.DISC.CS & BSY = 0 DO OD
CTL.ID => V.DISC.DATA;
SEL => V.DISC.CS;
WHILE V.DISC.CS & BSY /= 0 DO OD
@BOX 9.1
DMA => V.DISC.CS;
FOR I < 6 DO
  WHILE V.DISC.CS & BSY.CMD.REQ /= 0 DO OD
  CMD.BUFFER [I] => V.DISC.DATA;
OD
@BOX 6.1
END
@BOX 10.1
#AP502.4.1
@END
@TITLE AP502.4.1(4,11)
@COL 1S-2T-3T-4R-5R-6R-7R
@COL 8F

@ROW 8-4

@FLOW 1-2NO-3NO-4-5-6-7-2
@FLOW 2YES-8
@FLOW 3YES-8
@BOX 1.0
POLL EXCHANGEABLE DISCS
@BOX 2.0
NO MORE UNITS?
@BOX 3.0
POLL NOT REQUIRED YET?
@BOX 4.0
SET UP COMMAND BUFFER FOR
TEST READY COMMAND
@BOX 5.0
TRANSFER COMMAND
@BOX 6.0
READ STATUS
@BOX 7.0
NOTE ANY STATUS CHANGE
@BOX 8.0
END
@BOX 1.1
BEGIN
INTEGER UNIT;
LOGICAL STATUS;
-1 => UNIT;
@BOX 2.1
IF 1 +> UNIT >= SYS05.NO.OF.ED.UNITS
@BOX 3.1
SELECT DISC.VARS [UNIT + NO.OF.DRUM.SECTIONS];
IF POLL.REQ [UNIT] = 0 OR
   DISC.STATUS & %F00 /= 0 OR
   DISC.STATUS -= VV.DISC.CONTROL [UNIT] & 3 /= 0
@BOX 4.1
0 => POLL.REQ [UNIT];
FOR I < 6 DO
   0 => CMD.BUFFER [I];
OD
DRIVE.NO [UNIT + NO.OF.DRUM.SECTIONS] <<- 5 => CMD.BUFFER [1];
@BOX 5.1
CTL.ID => V.DISC.DATA;
SEL => V.DISC.CS;
WHILE V.DISC.CS & BSY /= 0 DO OD
0 => V.DISC.CS;
FOR I < 6 DO
   WHILE V.DISC.CS & BSY.CMD.REQ /= 0 DO OD
   CMD.BUFFER [I] => V.DISC.DATA;
OD
@BOX 6.1
FOR I < 2 DO
   WHILE V.DISC.CS & BSY.CMD.REQ /= 0 DO OD
   STATUS <<- 8 => STATUS;
   V.DISC.DATA !> STATUS;
OD
@BOX 7.1
IF STATUS & %0008 = 0 THEN
   IF DISC.STATUS & %8000 = 0 THEN
      %8800 !> DISC.STATUS;
      IF DISC.STATUS & 3 /= 0 THEN
         %200 !> DISC.STATUS;
      FI
   FI
ELSE
   IF DISC.STATUS & %8000 /= 0 THEN
      %8000 -=> DISC.STATUS;
      %800 !> DISC.STATUS;
      1 <<- SECTOR.SHIFT => VV.DISC.SIZE [UNIT];
      DISC.SIZES [DISC.TYPE [UNIT + NO.OF.DRUM.SECTIONS]] => VV.DISC.DADDRESS [U
NIT];
   FI
FI
IF DISC.STATUS & %800 /= 0 THEN
   IF 1 +> HW.INT.COUNT = 1 THEN
      SET.HW.INT (SYS01.DISC.ACTIVITY);
   FI
   DISC.STATUS  => VV.DISC.CONTROL [UNIT];
FI
@BOX 8.1
END
@END
@END

@TITLE AP502.5(4,11)

@COL 1S-2T-3R-4R-5F
@FLOW 1-2NO-3-4-5
@FLOW 2YES-5
@BOX 1.0
ED POLL
@BOX 2.0
WAIT NOT ENDED?
@BOX 3.0
NOTE POLL REQUIRED
@BOX 4.0
START TRANSFER
@BOX 5.0
END
@BOX 1.1
PROC ED.POLL;
INTEGER I;
@BOX 2.1
IF 1 +> POLL.WAIT < 3
@BOX 3.1
0 => POLL.WAIT;
FOR I < SYS05.NO.OF.ED.UNITS DO
   IF DISC.TYPE [I + NO.OF.DRUM.SECTIONS] /= -1 THEN
      1 => POLL.REQ [I];
   FI
OD
@BOX 4.1
START.TRANSFER ();
@BOX 5.1
END
@END


